Sattar, S. and Zulkifli, T.Z.A. (2017) A 2.4/5.2-GHz Concurrent Dual-Band CMOS Low Noise Amplifier. IEEE Access, 5. pp. 21148-21156. ISSN 21693536
Full text not available from this repository.Abstract
A concurrent dual-band low-noise amplifier (LNA) targeted for W-LAN IEEE 802.11 a/b/g standards is designed using 0.13- μm CMOS process. To attain the power-constrained simultaneous noise and input matching at 2.4 and 5.2 GHz, cascode common source inductive degeneration topology is adopted. The LNA achieves input reflection coefficients of -16.8 and -19.4 dB, forward gains of 19.3 and 17.5 dB at 2.4 and 5.2 GHz, respectively. Furthermore, the LNA exhibits noise figures of 3.2 and 3.3 dB with input 1-dB compression points of -29.6 and -28.2 dBm, while third-order input intercept points of -20.1 and -18.1 dBm at 2.4 and 5.2 GHz, respectively. The LNA dissipates 2.4 mW of power from a 1.2-V supply. © 2013 IEEE.
Item Type: | Article |
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Additional Information: | cited By 32 |
Uncontrolled Keywords: | Amplifiers (electronic); Capacitance; CMOS integrated circuits; Electric impedance; Electric power utilization; Impedance matching (electric); Logic gates; Natural frequencies; Standards; Wireless local area networks (WLAN), CMOS low noise amplifiers; Dual Band; Dual-band low noise amplifier; High gain; Input reflection coefficient; Low-power consumption; Power demands; Third-order input intercept points, Low noise amplifiers |
Depositing User: | Mr Ahmad Suhairi UTP |
Date Deposited: | 09 Nov 2023 16:20 |
Last Modified: | 09 Nov 2023 16:20 |
URI: | https://khub.utp.edu.my/scholars/id/eprint/8368 |