This paper presents a peak-triggered sampling scheme for future cochlear implants that aim to reserve temporal fine structure in the neural stimulation pulses. To address the low-power and small-area challenge for such application, the asynchronous delta modulation techniques are used to implement the scheme in VLSI circuitry. Simulation results show that the proposed circuitry achieves the required stimulation encoding function with less than 7μW power consumption and only 0.004mm2 area occupation, which makes it a promising candidate to implement future fine-structure-aware cochlear implant stimulation strategy. © 2017 IEEE.