Resistive open faults detectability analysis and implications for testing low power nanometric ICs

Mohammadat, M.T. and Ali, N.B.Z. and Hussin, F.A. and Zwolinski, M. (2015) Resistive open faults detectability analysis and implications for testing low power nanometric ICs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23 (3). pp. 580-583. ISSN 10638210

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Abstract

Resistive open faults (ROFs) represent common manufacturing defects in IC interconnects and result in delay faults that cause timing failures and reliability risks. The nonmonotonic dependence of ROF-induced delay faults on the supply voltage (VDD) poses a concern as to whether single-VDD testing will suffice for low power nanometric designs. Our analysis shows multi-VDD tests could be required, depending on the test speed. This knowledge can be exploited in small delay fault testing to reduce the chances of test escapes while minimizing cost. © 1993-2012 IEEE.

Item Type: Article
Additional Information: cited By 2
Uncontrolled Keywords: Electric power supplies to apparatus, Delay faults; Detectability; Low-power design; Resistive open; variability, Integrated circuit interconnects
Depositing User: Mr Ahmad Suhairi UTP
Date Deposited: 09 Nov 2023 16:17
Last Modified: 09 Nov 2023 16:17
URI: https://khub.utp.edu.my/scholars/id/eprint/6000

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