Koko, I.S. and Agustiawan, H. (2009) Parallel pipelined VLSI architectures for lifting-based two-dimensional forward discrete wavelet transform. In: UNSPECIFIED.
Full text not available from this repository.Abstract
In this paper, in order to best meet real-time applications of 2-dimensional discrete wavelet transform (2-D DWT) with demanding requirements in terms of speed and throughput, 2-parallel and 4-parallel pipelined lifting-based VLSI architectures for lossless 5/3 and lossy 9/7 algorithms are proposed. The two proposed parallel architectures achieve speedup factors of 2 and 4 as compared with single pipelined architecture based on the first scan method proposed by Ibrahim et al. The advantage of the proposed architectures is that they only require a total temporary line buffer (TLB) of size N and 3N in 5/3 and 9/7, respectively. © 2009 IEEE.
Item Type: | Conference or Workshop Item (UNSPECIFIED) |
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Additional Information: | cited By 1; Conference of 2009 International Conference on Signal Acquisition and Processing, ICSAP 2009 ; Conference Date: 3 April 2009 Through 5 April 2009; Conference Code:79615 |
Uncontrolled Keywords: | Discrete wavelets; Forward discrete wavelet transforms; JPEG 2000; Lifting schemes; Lossless; Parallel VLSI architectures; Pipelined architecture; Proposed architectures; Real-time application; Scan methods; Speed-up factors; VLSI architectures, Decoding; Digital image storage; Discrete wavelet transforms; Parallel architectures; Signal analysis, Signal processing |
Depositing User: | Mr Ahmad Suhairi UTP |
Date Deposited: | 09 Nov 2023 15:48 |
Last Modified: | 09 Nov 2023 15:48 |
URI: | https://khub.utp.edu.my/scholars/id/eprint/599 |