Automatic generation of test instructions for structural faults in processor cores using satisfiability

Shaheen, A.-U.-R. and Hussin, F.A. and Hamid, N.H. and Ali, N.B.Z. (2013) Automatic generation of test instructions for structural faults in processor cores using satisfiability. In: UNSPECIFIED.

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Abstract

Instruction execution from the cache to detect the faulty chips in native mode has proven its effectiveness with high performance and low power consumption. Gate-level ATPG are time expensive and difficult to implement for large design. In this paper, we proposed an RTL-based methodology framework to generate the test program based on instructions set architecture (ISA) to test structural faults in processor cores. The proposed methodology framework made three major contributions. First, the use of effective conjunctive normal formula (CNF) encoding and instruction set architecture (ISA) prunes the combinational and sequential search space. Second, the modular based test generation and use of instruction set architecture (ISA) considerably reduces the test generation time. Third, an automatic generation of test instructions for structural faults. © 2013 IEEE.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Additional Information: cited By 1; Conference of 2013 International SoC Design Conference, ISOCC 2013 ; Conference Date: 17 November 2013 Through 19 November 2013; Conference Code:107260
Uncontrolled Keywords: ATPG; BCP; CNF; ISA; RTL; SAT; SBST, Computer architecture
Depositing User: Mr Ahmad Suhairi UTP
Date Deposited: 09 Nov 2023 15:52
Last Modified: 09 Nov 2023 15:52
URI: https://khub.utp.edu.my/scholars/id/eprint/3809

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