High throughput architecture for low density parity check (LDPC) encoder

Anggraeni, S. and Hussin, F.A. and Jeoti, V. (2013) High throughput architecture for low density parity check (LDPC) encoder. In: UNSPECIFIED.

Full text not available from this repository.
Official URL: https://www.scopus.com/inward/record.uri?eid=2-s2....

Abstract

This paper proposes a bit-wise matrix-vector multiplication in the optimization of a proposed low density parity check (LDPC) encoder. Investigation of this proposed architecture is done by implementing five code lengths using one IEEE 802.16e standard code rate. It is shown that the proposed architecture outperforms other works in terms of information throughput ranging from 0.235 to 8.83 times higher. In term of ratio of throughput per area, the proposed method exceeds other works in the range of 1.19 to 6.54 times higher. © 2013 IEEE.

Item Type: Conference or Workshop Item (UNSPECIFIED)
Additional Information: cited By 1; Conference of 2013 IEEE 56th International Midwest Symposium on Circuits and Systems, MWSCAS 2013 ; Conference Date: 4 August 2013 Through 7 August 2013; Conference Code:102320
Uncontrolled Keywords: Code length; High throughput; Ieee 802.16e standards; Low density parity check; Matrix vector multiplication; Proposed architectures
Depositing User: Mr Ahmad Suhairi UTP
Date Deposited: 09 Nov 2023 15:51
Last Modified: 09 Nov 2023 15:51
URI: https://khub.utp.edu.my/scholars/id/eprint/3316

Actions (login required)

View Item
View Item