The error-sensitivity of nanoscale circuits is an extremely important issue in electronic industry these days. The reason is the high susceptibility of electronic circuits to noise at the nanoscale level. Markov Random Field (MRF) modelling is one approach to achieve noise-tolerance in integrated circuit design. In this paper, we have designed an error-detection mechanism for digital circuits based on Joint Probability analysis of Markov random Field (MRF) networks. The circuit and test bench design has been carried out in the software Xilinx ISE 8.1i. Our error-detection mechanism is an excellent solution for digital system designs where space is not a critical factor but reliability of system matters a lot. © 2012 IEEE.