Reliability has become an important design consideration for integrated circuits especially as CMOS dimension enters into the nanoscale regime. An ability to accurately measure reliability of CMOS circuits has become very crucial. Tools such as Probabilistic Gate Model (PGM), Boolean Difference-based Error Calculator (BDEC) and Probabilistic Transfer Matrix (PTM) have been developed to measure reliability of a given circuit. However, there has not been work done to determine the efficiency of these tools in giving not only accurate but transparent reliability measure. In this work, a general computational technique based on statistical dependency of circuit's input/output signals has been developed to validate the accurateness and correctness of the evaluation tools in computing reliability of selected benchmark test circuits. The computation is carried out by partitioning the benchmark test circuits. The reliability measures yield from these partitions are then evaluated for the selection of efficient tool. The statistical dependency-based method enables a simple yet competent way to conclude that PTM gives significantly adequate reliability measure compared to PGM and BDEC. Therefore, to obtain best circuit design with highest reliability measure, PTM modeling method would be the best consideration for reliability evaluation of nanoscale circuits. © 2012 IEEE.