Fault Diagnosis is important step in detecting manufacturing process problems and improving its quality. Characterizing the effect of faults on the performance of circuits is essential in diagnosing and testing faulty chips. Resistive opens are common manufacturing faults which affect the timing performance of circuits. In dynamic voltage scaling environment, the supply voltage and clock frequency are dynamically adjusted to meet the processing demands. With this awareness, we previously demonstrated that the delay caused by resistive opens as the V DD increases show different increment and decrement patterns depending on the range of the open resistance value. However, the path delay in CMOS circuits increases exponentially with reduced V DD. In this work, we investigate how the delay of the opens is propagated through the CMOS circuit. We show how this behavior is manifested with the aid of simulation on benchmark circuits based on 130nm technology model as well as 65nm, 22nm and 16nm Berkeley Predictive Technology Models (BPTM). Based on this observation and to ease fault related work on resistive open faults, we proposed dividing the full range of opens resistances into smaller subsets of resistance intervals. © 2011 IEEE.