The existing binary logic (two-level) and MOSFET (metal oxide semiconductor field effect transistor) have limitations in terms of storage density, chip area and interconnect limitations. To overcome these limitations, the concept of multiple valued logic (MVL) circuits is introduced. The ternary logic is one of the most effective implementation for design of multivalued logic circuits due to its reduced interconnect complexity and chip area. The design methodology for the implementation of 2-bit ternary comparator utilizing carbon nanotube field effect transistor (CNTFET) and resistive random access memory (RRAM)is presented in this manuscript. CNTFETs are preferred for design of ternary logic circuits due to its desirable property of adjusting the desired threshold voltage which is dependent on the the carbon nanotube (CNT) diameter. Additionally, another technology suitable for ternary design implementation is RRAM due to its ability to store multiple resistance states within a single cell. The ternary comparator has been designed using CNTFETRRAM ternary logic gates and utilizing negation of literals technique. The comparator design utilizes both binary and ternary gates for effective implementation. This paper presents the simulation results of the ternary comparator using HSPICE software. © 2021 IEEE.