Anwer, J. and Khalid, U. and Singh, N. and Hamid, N.H. and Asirvadam, V.S. (2010) Highly noise-tolerant design of digital logic gates using Markov random field modelling. In: UNSPECIFIED.
Full text not available from this repository.Abstract
Current trend of downscaling CMOS transistor dimensions is increasing the liability of digital circuits to be easily affected by noise. The resulting unexpected behaviour of our digital devices is due to the low supply voltage of these downscaled circuit elements. Though the low supply voltage decreases the power dissipation of a circuit to a great extent, it decreases the signal to noise ratio as well. The need to transform the conventional logic gates into modified ones having the same functionality but are highly noise-tolerant is catered by the technique Markov Random Field (MRF) modelling proposed in 1. This paper contributes towards explaining MRF design in a simplified form, proves the error tolerant capability of MRF circuits by simulations performed in Cadence (simulation software) and finally proposes an improvement in the design of 1. ©2010 IEEE.
Item Type: | Conference or Workshop Item (UNSPECIFIED) |
---|---|
Additional Information: | cited By 6; Conference of 2010 International Conference on Electronic Computer Technology, ICECT 2010 ; Conference Date: 7 May 2010 Through 10 May 2010; Conference Code:80919 |
Uncontrolled Keywords: | Circuit elements; CMOS transistors; Current trends; Digital logic gates; Down-scaling; Energy functions; Error tolerant; Joint probability; Low supply voltages; Markov random field; Markov Random Fields; Noise-Tolerant; Noise-tolerant design; Power dissipation; Simulation software, Computer software; Computers; Design; Digital devices; Digital integrated circuits; Logic gates; Signal to noise ratio; Wavelet transforms, Probabilistic logics |
Depositing User: | Mr Ahmad Suhairi UTP |
Date Deposited: | 09 Nov 2023 15:49 |
Last Modified: | 09 Nov 2023 15:49 |
URI: | https://khub.utp.edu.my/scholars/id/eprint/1211 |